Title :
Programmable switched-capacitor bump equalizer architecture
Author :
Duque-Carrillo, J. Francisco ; Silva-Martínez, José ; SÁnchez-Sinencio, Edgar
fDate :
8/1/1990 12:00:00 AM
Abstract :
A versatile and economical switched-capacitor (SC) equalizing structure to compensate attenuation characteristics is presented. The monolithic SC bump equalizer has three operational amplifiers and six capacitor banks to independently control the center frequency, bandwidth, and peak voltage gain steps for the bump (and dip) frequency response. The bump equalizer has been integrated using 3-μm CMOS (p-well) technology and occupies an area of 3.36 mm2, including an additional test amplifier and test buffer. The circuit operating from ±5-V power supplies typically dissipates 60 mW when sampled at 75 kHz
Keywords :
CMOS integrated circuits; active networks; equalisers; frequency response; switched capacitor networks; 5 V; 60 mW; 75 kHz; CMOS; attenuation characteristics compensation; bandwidth; bump equalizer architecture; capacitor banks; center frequency; frequency response; operational amplifiers; p-well; peak voltage gain steps; programmable SC circuit; switched-capacitor; Attenuation; Bandwidth; CMOS technology; Capacitors; Circuit testing; Equalizers; Frequency; Operational amplifiers; Power generation economics; Voltage control;
Journal_Title :
Solid-State Circuits, IEEE Journal of
