DocumentCode
1547032
Title
Experimental confirmation of an accurate CMOS gate delay model for gate oxide and voltage scaling
Author
Kai Chen ; Chenming Hu ; Peng Fang ; Gupta, A.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Volume
18
Issue
6
fYear
1997
fDate
6/1/1997 12:00:00 AM
Firstpage
275
Lastpage
277
Abstract
MOSFET´s and CMOS ring oscillators with gate oxide thicknesses from 2.58 nm to 5.7 nm and effective channel lengths down to 0.21 μm have been studied at voltages from 1.5 V to 3.3 V. Physical and electrical measurement of gate oxide thicknesses are compared. Ring oscillators´ load capacitance is characterized through dynamic current measurement. An accurate model of CMOS gate delay is compared with measurement data. It shows that the dependence of gate propagation delay on gate oxide, channel length, and voltage scaling can be predicted.
Keywords
CMOS integrated circuits; MOSFET; capacitance; carrier mobility; delays; integrated circuit measurement; integrated circuit modelling; 0.21 mum; 1.5 to 3.3 V; 2.58 to 5.7 nm; CMOS gate delay model; CMOS ring oscillators; MOSFET; dynamic current measurement; effective channel lengths; electrical measurement; gate oxide scaling; gate oxide thicknesses; gate propagation delay; physical measurement; ring oscillator load capacitance; voltage scaling; Capacitance; Current measurement; Dynamic voltage scaling; Electric variables measurement; Length measurement; Propagation delay; Ring oscillators; Semiconductor device modeling; Thickness measurement; Voltage-controlled oscillators;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.585355
Filename
585355
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