A reduced-area low-power low-voltage single-ended differential pair

Author

Mulder, J. ; de Gevel, M. van ; van Roermund, A.H.M.

Author_Institution

Lab. of Electron. Res., Delft Univ. of Technol., Netherlands

Volume

32

Issue

2

fYear

1997

fDate

2/1/1997 12:00:00 AM

Firstpage

254

Lastpage

257

Abstract

In analog very large scale integration (VLSI), a high computational density is important. Area savings can be obtained by operating the MOS transistor in the triode region, thus exploiting its symmetrical nature. Applying this theory to a single-ended differential pair results in an area reduction of up to a factor 1.5, which can be significant, e.g., for neural networks, where the basic cells are repeated many times on a single chip. The proposed circuit also has advantages with respect to low-power and low-voltage operation

Keywords

CMOS analogue integrated circuits; VLSI; analogue processing circuits; neural chips; CMOS ICs; MOS transistor; MOSFET triode region operation; analog VLSI; chip area reduction; high computational density; low-power operation; low-voltage operation; reduced-area differential pair; single-ended differential pair; very large scale integration; Analog computers; CMOS analog integrated circuits; Computer networks; Equations; MOSFETs; Neural network hardware; Neural networks; Neurons; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.551919

Filename

551919