Title :
Optimizing quarter and sub-quarter micron CMOS circuit speed considering interconnect loading effects
Author :
Chen, Kai ; Hu, Chenming ; Fang, Peng ; Lin, Min Ren ; Wollesen, Donald L.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
9/1/1997 12:00:00 AM
Abstract :
An experimentally confirmed accurate CMOS gate delay model is applied to the CMOS ring oscillators with interconnect loading. The optimum gate oxide thickness Tox should be chosen differently as interconnect loading varies. Guidelines in choosing optimum Tox for different interconnect loading, combined with channel length and power supply scaling, are obtained
Keywords :
CMOS digital integrated circuits; VLSI; capacitance; circuit optimisation; delays; integrated circuit interconnections; integrated circuit measurement; integrated circuit modelling; CMOS circuit speed; VLSI; channel length; gate delay model; gate oxide thickness; interconnect loading effects; power supply scaling; ring oscillators; Capacitance measurement; Equations; Integrated circuit interconnections; Notice of Violation; Plasma devices; Power supplies; Propagation delay; Quantum capacitance; Ring oscillators; Semiconductor device modeling;
Journal_Title :
Electron Devices, IEEE Transactions on
