State-of-the-Art and Future Directions of High-Performance All-Digital Frequency Synthesis in Nanometer CMOS

The past several years have successfully brought all-digital techniques to the RF frequency synthesis, which could arguably be considered one of the last strong bastions of the traditionally-analog design approaches. With their high sensitivity and high dynamic range requirements, the RF circuits have long had a good excuse to avoid any possible source of digital switching activity. With the constant scaling of CMOS feature size and the merciless push for integration, the existence of almost free and powerful digital logic could not go unnoticed. Hence, the environment was ripe to transform the RF functions into digital realizations, as well as to apply digital assistance to help with the performance of RF circuits. This paper revisits the digitization journey of the traditional charge-pump PLL that has resulted in an all-digital frequency synthesizer with the best-in-class RF performance while occupying only a fraction of the silicon area and consuming a fraction of the power. The paper also offers a few novel techniques to further improve area, current consumption, testability, and reliability of frequency synthesizers.