Title :
Efficient method for simulating time delays of distributed interconnections in VLSI circuits
Author :
Maffezzoni, P. ; Brambilla, A.
Author_Institution :
Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
fDate :
6/10/1999 12:00:00 AM
Abstract :
A new technique is described for modelling a general distributed RC line through a simple lumped net. This reduced order model approximates both the long time voltage response and the input loading effect of the line. The proposed method has the advantage of allowing the employment of circuit simulators such as SPICE to evaluate interconnect delays in complex layouts
Keywords :
RC circuits; SPICE; VLSI; circuit simulation; delays; equivalent circuits; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; SPICE; VLSI circuits; circuit simulators; distributed interconnections; general distributed RC line; input loading effect; interconnect delays; lumped net; reduced order model; time delays; time voltage response;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19990702
