Title :
Optimization of 40-nm Node Epitaxial Diode Array for Phase-Change Memory Application
Author :
Liu, Yan ; Song, Zhitang ; Liu, Bo ; Wu, Guanping ; Chen, Houpeng ; Zhang, Chao ; Wang, Lianhong ; Feng, Songlin
Author_Institution :
State Key Lab. of Functional Mater. for Inf., Shanghai Inst. of Microsyst. & Inf. Technol., Shanghai, China
Abstract :
A numerical model of an epitaxial (EPI) diode array for next-generation memory device application, including phase-change memory, has been presented. According to a diode array process scheme and technology computer-aided design (TCAD) simulation results, a quasi-physical model with a buried n+ layer dosage, EPI layer thickness, and breakdown voltage (BVD) correlation is proposed to improve electrical performance. From the optimal silicon-based results, a 16×16 diode array shows a drive current density of ~56.6 mA/μm2, a BVD of ~8 V, a Jon/Joff ratio of ~109, and crosstalk immunity. Additionally, this calibrated physical model can be applied in the next generation of silicon-based fabrication with parameters extraction.
Keywords :
electric breakdown; elemental semiconductors; numerical analysis; phase change memories; silicon; technology CAD (electronics); BVD; EPI layer thickness; Si; TCAD simulation; breakdown voltage correlation; buried n+ layer dosage; crosstalk immunity; electrical performance improvement; epitaxial diode array; next-generation memory device application; numerical model; parameters extraction; phase-change memory application; quasiphysical model; silicon-based fabrication; size 40 nm; technology computer-aided design simulation; Arrays; Doping; Numerical models; Phase change materials; Phase change memory; Resistance; Silicon; Buried $hbox{n}^{+}$ layer (BNL) series resistance; epitaxial (EPI) diode array; numerical model; phase-change memory (PCM);
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2012.2199733
