DocumentCode
1554956
Title
Parallel signature analysis design with bounds on aliasing
Author
Saxena, Nirmal R. ; McCluskey, Edward J.
Volume
46
Issue
4
fYear
1997
fDate
4/1/1997 12:00:00 AM
Firstpage
425
Lastpage
438
Abstract
This paper presents parallel signature design techniques that guarantee the aliasing probability to be less than 2/L, where L is the test length. Using y signature samples, a parallel signature analysis design is proposed that guarantees the aliasing probability to be less than (y/L)y/2. Inaccuracies and incompleteness in previously published bounds on the aliasing probability are discussed. Simple bounds on the aliasing probability are derived for parallel signature designs using primitive polynomials
Keywords
logic CAD; logic testing; polynomials; signal processing; aliasing; bounds; incompleteness; parallel signature analysis design; primitive polynomials; Automatic testing; Built-in self-test; Circuit testing; Compaction; Guidelines; Helium; Linear feedback shift registers; Polynomials; System testing; Very large scale integration;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.588057
Filename
588057
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