• DocumentCode
    1558048
  • Title

    Parameterized RTL power models for soft macros

  • Author

    Bogliolo, Alessandro ; Corgnati, Roberto ; Macii, Enrico ; Poncino, Massimo

  • Author_Institution
    Ferrara Univ., Italy
  • Volume
    9
  • Issue
    6
  • fYear
    2001
  • Firstpage
    880
  • Lastpage
    887
  • Abstract
    We propose a new power macromodel for usage in the context of register-transfer level (RTL) power estimation. The model is suitable for reconfigurable, synthesizable, soft macros because it is parameterized with respect to the input data size (i.e., bit width) and can also be automatically scaled with respect to different technology libraries and/or synthesis options. The power model is precharacterized once and for all for each soft macro and then adapted to each specific instance by means of a single additional experiment to be performed by the end user. No intellectual-property disclosure is required for model scaling. The proposed model is derived from empirical analysis of the sensitivity of power consumption on input statistics, input data size, and technology. The experiments prove that with limited approximation, it is possible to decouple the effects on power of these three factors. The proposed solution is innovative since no previous macromodel supports automatic technology scaling and yields average estimation errors around 10%.
  • Keywords
    cellular arrays; combinational circuits; logic CAD; logic arrays; low-power electronics; power consumption; sequential circuits; Synopsys DesignWare Library; combinational macros; intellectual property protection; library macrocells; low-power design; low-power dissipation; model scaling; parameterized RTL power models; parameterized accumulator; power consumption model; power macromodel; register-transfer level power estimation; sequential macros; soft macros; Costs; Energy consumption; Estimation error; Libraries; Macrocell networks; Runtime; Statistical analysis; Statistics; Structural engineering; Uncertainty;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/92.974901
  • Filename
    974901