Title :
Implementing ASIC/memory integration by system-on-package
Author :
Tsai, R.B. ; Lu, Ray ; Lin, C.L. ; Chen, S.K. ; Tsai, Fang-Jeng ; Tseng, Kuo-Tai
Author_Institution :
ChipMOS Technol. Inc., Tainan, Taiwan
fDate :
12/1/2001 12:00:00 AM
Abstract :
A system-on-package (SOP) solution of an application specific integrated circuit (ASIC) chip integrating with an embedded data output (EDO) memory die has been realized. Both chips are assembled into a new form factor that appears as a standard plastic ball grid array (PBGA) with 90 balls and 1.27 mm ball pitch. Topically, size reduction of approximately 60% over the equivalent printed circuit board implementation is achieved. Other benefits include simplified board design and reduction in material cost. Assembly processes are expressed to indicate how this package is made. Reliability analyzes such as: pre-conditioning, temperature cycle test (TCT), and pressure cook test (PCT), are conducted
Keywords :
application specific integrated circuits; ball grid arrays; integrated circuit packaging; integrated circuit reliability; life testing; moulding; plastic packaging; 1.27 mm; application specific integrated circuit; assembly processes; board design; embedded data output memory die; form factor; material cost; multichip package; pre-conditioning; pressure cook test; standard plastic ball grid array size reduction; system-on-package; temperature cycle test; Application specific integrated circuits; Assembly; Circuit testing; Costs; Electronics packaging; Integrated circuit packaging; Plastic integrated circuit packaging; Plastic packaging; Random access memory; System-on-a-chip;
Journal_Title :
Components and Packaging Technologies, IEEE Transactions on
DOI :
10.1109/6144.974954
