Title :
Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm
Author :
Barraud, S. ; Berthomé, M. ; Coquand, R. ; Cassé, M. ; Ernst, T. ; Samson, M.-P. ; Perreau, P. ; Bourdelle, K.K. ; Faynot, O. ; Poiroux, T.
Author_Institution :
LETI, Commissariat a l´´Energie Atomique et aux Energies Alternatives, Grenoble, France
Abstract :
In this letter, we report the performance of high-κ /metal gate nanowire (NW) transistors without junctions fabricated with a channel thickness of 9 nm and sub-15-nm gate length and NW width. Near-ideal subthreshold slope (SS) and extremely low leakage currents are demonstrated for ultrascaled gate lengths with a high on-off ratio (Ion/Ioff) >; 106. For the first time, an SS lower than 70 mV/dec is achieved at LG = 13 nm for n-type and p-type transistors, highlighting excellent electrostatic integrity of trigate junctionless NW MOSFETs.
Keywords :
MOSFET; high-k dielectric thin films; leakage currents; nanoelectronics; nanowires; electrostatic integrity; high on-off ratio; high-κ-metal gate nanowire transistors; leakage currents; n-type transistors; near-ideal subthreshold slope; p-type transistors; size 13 nm; size 9 nm; trigate junctionless nanowire MOSFET scaling; ultrascaled gate lengths; Doping; Electrostatics; Logic gates; MOSFET circuits; Silicon; Threshold voltage; Transistors; Accumulation mode; MOSFET; junctionless (JL); nanowire (NW); scaling; trigate;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2012.2203091
