DocumentCode :
1558781
Title :
Pin assignment with global routing for general cell designs
Author :
Cong, Jingsheng
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Volume :
10
Issue :
11
fYear :
1991
fDate :
11/1/1991 12:00:00 AM
Firstpage :
1401
Lastpage :
1412
Abstract :
The author presents an algorithm which combines the pin assignment step and the global routing step in the physical design of VLSI circuits. The algorithm is based on two key theorems: the channel pin assignment theorem and the block boundary decomposition theorem. These two theorems deal successfully with the high complexity resulting from combining the pin assignment and global routing steps. According to these two theorems, one only needs to generate a coarse pin assignment and global routing solution. The exact pin locations and global routing topology can be determined optimally later by a linear time algorithm. The author implemented a pin assignment and global routine package named BeauticianGR based on the proposed algorithm. This package produces satisfactory results on test circuits
Keywords :
VLSI; circuit layout CAD; graph theory; integrated circuit technology; network topology; BeauticianGR; CAD; IC layout design; VLSI circuits; block boundary decomposition theorem; channel pin assignment theorem; global routing; linear time algorithm; routing topology; Algorithm design and analysis; Automatic testing; Circuit testing; Circuit topology; Joining processes; Pins; Process design; Routing; Semiconductor device packaging; Very large scale integration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.97619
Filename :
97619
Link To Document :
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