Title :
Differential CMOS edge-triggered flip-flop with clock-gating
Author :
Xia, Y. ; Almaini, A.E.A.
Author_Institution :
Sch. of Eng., Napier Univ. of Edinburgh, UK
fDate :
1/3/2002 12:00:00 AM
Abstract :
A non-redundant transition clock chain is proposed and applied to differential edge-triggered flip-flops. PSPICE simulation shows that compared to a recently published design the proposed circuit can save power when the switching activity of the input signal is <0.65. Power reduction can be as high as 86% when the input is idle
Keywords :
CMOS logic circuits; SPICE; clocks; flip-flops; low-power electronics; CMOS flip-flop; PSPICE simulation; cascaded transistors; clock-gating; differential edge-triggered flip-flops; nonredundant transition clock chain; power reduction;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20020038
