DocumentCode :
1559031
Title :
Differential CMOS edge-triggered flip-flop with clock-gating
Author :
Xia, Y. ; Almaini, A.E.A.
Author_Institution :
Sch. of Eng., Napier Univ. of Edinburgh, UK
Volume :
38
Issue :
1
fYear :
2002
fDate :
1/3/2002 12:00:00 AM
Firstpage :
9
Lastpage :
11
Abstract :
A non-redundant transition clock chain is proposed and applied to differential edge-triggered flip-flops. PSPICE simulation shows that compared to a recently published design the proposed circuit can save power when the switching activity of the input signal is <0.65. Power reduction can be as high as 86% when the input is idle
Keywords :
CMOS logic circuits; SPICE; clocks; flip-flops; low-power electronics; CMOS flip-flop; PSPICE simulation; cascaded transistors; clock-gating; differential edge-triggered flip-flops; nonredundant transition clock chain; power reduction;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:20020038
Filename :
977521
Link To Document :
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