Title :
Power model for DCFL family
Author :
García, J. ; Hernández, A. ; del Pino, J. ; Sendra, J.R. ; González, B. ; Nunez, A.
Author_Institution :
Appl. Microelectron. Res. Inst., Univ. of Las Palmas de Gran Canaria, Spain
fDate :
1/3/2002 12:00:00 AM
Abstract :
A model to estimate power consumption in GaAs direct coupled FET logic (DCFL) family, which is based on sensitivity computations, is reported. Comparisons against SPICE simulations show errors smaller than 5% in power consumption estimation, while CPU time is reduced by more than two orders of magnitude
Keywords :
III-V semiconductors; JFET integrated circuits; SPICE; direct coupled FET logic; field effect logic circuits; gallium arsenide; integrated circuit modelling; power consumption; sensitivity analysis; GaAs; SPICE simulations; Taylor expansion; direct coupled FET; heterostructure field effect transistors; power consumption; power model; reduced CPU time; second-order partial derivatives; sensitivity computations; static current; total current;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20020027
