Compact diamond MOSFET model accounting for PAMDLE applicable down 150 nm node

Author

Gimenez, Salvador Pinillos ; Davini, E. ; Peruzzi, V.V. ; Renaux, Christian ; Flandre, Denis

Author_Institution

Electr. Eng. Dept., FEI Univ. Center, São Bernardo do Campo, Brazil

Volume

50

Issue

22

fYear

2014

fDate

10 23 2014

Firstpage

1618

Lastpage

1620

Abstract

The performance improvements for integrated circuit applications of silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistors (MOSFETs) implemented with diamond layout style (hexagonal gate geometry) are quantified, thanks to the longitudinal corner effect and parallel association of MOSFETs with different channel lengths effect contributions. Futhermore, an accurate analytical drain current model for planar diamond SOI MOSFET for micrometre scale effective channel lengths is proposed and validated. The concept is then extended by 3D simulations for the 150 nm node fully-depleted SOI n-channel MOSFETs.

Keywords

MOSFET; diamond; geometry; integrated circuit layout; silicon-on-insulator; 3D simulations; IC applications; LCE; PAMDLE applicable down node; analytical drain current model; channel lengths effect contributions; diamond layout style; fully-depleted SOI n-channel MOSFET; hexagonal gate geometry; integrated circuit applications; longitudinal corner effect; metal-oxide semiconductor field-effect transistors; micrometre scale effective channel lengths; parallel association; performance improvements; planar diamond; silicon-on-insulator; size 150 nm; three-dimensional simulations;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el.2014.1229

Filename

6937274