Title :
Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel
Author :
Yeo, Yee-Chia ; Subramanian, Vivek ; Kedzierski, Jakub ; Xuan, Peiqi ; King, Tsu-Jae ; Bokor, Jeffrey ; Hu, Chenming
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
2/1/2002 12:00:00 AM
Abstract :
Thin-body p-channel MOS transistors with a SiGe/Si heterostructure channel were fabricated on silicon-on-insulator (SOI) substrates. A novel lateral solid-phase epitaxy process was employed to form the thin-body for the suppression of short-channel effects. A selective silicon implant that breaks up the interfacial oxide was shown to facilitate unilateral crystallization to form a single crystalline channel. Negligible threshold voltage roll-off was observed down to a gate length of 50 nm. The incorporation of Si0.7Ge0.3 in the channel resulted in a 70% enhancement in the drive current. This is the smallest SiGe heterostructure-channel MOS transistor reported to date. This is also the first demonstration of a thin-body MOS transistor incorporating a SiGe heterostructure channel
Keywords :
Ge-Si alloys; MOSFET; crystallisation; ion implantation; semiconductor heterojunctions; semiconductor materials; silicon-on-insulator; solid phase epitaxial growth; 50 nm; SOI substrate; Si0.7Ge0.3-Si; SiGe/Si heterostructure channel; design; drive current; fabrication; interfacial oxide; lateral solid-phase epitaxy; selective silicon implant; short-channel effect; thin-body p-MOSFET; threshold voltage roll-off; unilateral crystallization; Crystallization; Epitaxial growth; Fabrication; Germanium silicon alloys; Implants; MOSFET circuits; Silicon germanium; Silicon on insulator technology; Substrates; Threshold voltage;
Journal_Title :
Electron Devices, IEEE Transactions on