Title :
Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit
Author :
Ker, Ming-Dou ; Tsai, Chia-Sheng
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
This paper presents a 2.5 V/5 V mixed-voltage CMOS I/O buffer that does not need a CMOS technology with a dual-oxide option and complex bias circuits. The proposed mixed-voltage I/O buffer with simpler circuit structure can overcome the problems of leakage current and gate-oxide reliability, which occurring in the conventional CMOS I/O buffer. In this work, the new proposed design has been realized in a 0.25 μm CMOS process, but it can be easily scaled toward 0.18 μm or 0.15 μm processes to serve a 1.8 V/3.3 V mixed-voltage I/O interface.
Keywords :
CMOS integrated circuits; buffer circuits; low-power electronics; 0.25 micron; 2.5 V; 5 V; dynamic N-well bias circuit; gate oxide reliability; leakage current; low-voltage design; mixed-voltage CMOS I/O buffer circuit; thin oxide device; CMOS process; CMOS technology; Circuits; Diodes; Electric breakdown; Leakage current; MOS devices; Nanoelectronics; Power supplies; Voltage;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206197
