Title :
Optimal use of 2-phase transparent latches in buffered maze routing
Author_Institution :
Tufts Univ., Medford, MA, USA
Abstract :
Clocking frequencies continue to increase due to the demand for higher performance. Together with the larger die sizes, multiple clock cycles are now required to cross a chip. A routing tool must thus insert registers as well as buffers while minimizing the path latency. This paper addresses optimal buffered path construction across multiple clock cycles using 2-phase transparent latches. We demonstrate the benefits of routing using latches over registers, and we present a polynomial routing algorithm. Our results confirm the correctness of our algorithm.
Keywords :
circuit layout CAD; circuit optimisation; clocks; flip-flops; integrated circuit layout; logic CAD; network routing; polynomials; system-on-chip; 2-phase transparent latches; CAD tools; SoC designs; VLSI design; buffer insertion; buffered maze routing; clocking frequencies; multiple clock cycles; optimal buffered path construction; path latency minimization; polynomial routing algorithm; register insertion; routing graph; routing tool; Clocks; Delay; Frequency; Latches; Partitioning algorithms; Polynomials; Registers; Routing; Time measurement; Wire;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206207
