Process characteristics of 100 /spl mu/m bump pitch with lead-free and high lead plating solder bump

Author

Yu, Rick ; Jui-I Yu ; Tai, Tom ; Kang, CH ; Chen, Jami ; Taguibao, Jowel ; Tsai, Mars ; Tong, Homing ; Hsieh, Ker-Chang

Author_Institution

Adv. Semicond. Eng. Inc., Kaohsiung

Volume

2

fYear

2005

Abstract

A technique for 100 mum fine pitch bump process characteristics with stack thin film as under bump metallization structure, such as Ti/Cu/Ni and Ti/NiV/Cu were investigated and appropriated these UBM structure for height density solder bump as interconnect applications. Plating bump process characteristics capability available to develop the high amount I/O of solder bump can meet a requirement for next generation flip chip package. Solder bumps were formed after reflowing eutectic Sn/Ag and 5Sn95Pb solder foils over the two kinds of UBM structure; the reliability of these solder bump was evaluated with multireflow process test and solder bump shear strength measurement; the intermetallic compound formation between SnPb and thin film of these metals have been considered and compared with UBM cross-sectional image by SEM inspection. The best bump metallization structure selection will be addressed to make the flip chip package success

Keywords

copper alloys; eutectic alloys; fine-pitch technology; flip-chip devices; integrated circuit metallisation; integrated circuit reliability; lead alloys; nickel alloys; reflow soldering; shear strength; silver alloys; tin alloys; titanium alloys; 100 micron; SEM inspection; Sn-Ag; SnPb; Ti-Cu-Ni; bump pitch; eutectic solder foils; fine pitch bump process characteristics; flip chip package; high lead plating solder bump; interconnect applications; intermetallic compound formation; lead-free solder bump; multireflow process test; reflow soldering; shear strength measurement; stack thin film; under bump metallization structure; Environmentally friendly manufacturing techniques; Flip chip; Intermetallic; Lead; Metallization; Packaging; Semiconductor device measurement; Testing; Tin; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Packaging Technology Conference, 2005. EPTC 2005. Proceedings of 7th

Conference_Location

Singapore

Print_ISBN

0-7803-9578-6

Type

conf

DOI

10.1109/EPTC.2005.1614455

Filename

1614455