Title :
Area and power optimization of FPRM function based circuits
Author :
Xia, Y. ; Ali, B. ; Almaini, A.E.A.
Author_Institution :
Napier Univ. of Edinburgh, UK
Abstract :
In this paper, a frame of power dissipation estimation for FPRM function based circuits is presented and polarity conversion is proposed to optimize power and area for Fixed Polarity Reed-Muller (FPRM) functions. Based on searching optimized polarity, an optimized algorithm is proposed and implemented in C. The algorithm is tested on MCNC benchmark circuits. Experimental results show a significant reduction of power dissipation without area penalty or with small area penalty compared to those from previous publications.
Keywords :
CMOS logic circuits; circuit optimisation; integrated circuit design; logic design; low-power electronics; C implemented optimization algorithm; FPRM function based circuits; area optimization; fixed polarity Reed-Muller functions; polarity conversion; power dissipation estimation; power dissipation reduction; power optimization; search optimized polarity; Benchmark testing; CMOS digital integrated circuits; Capacitance; Circuit testing; Delay estimation; Equations; Field programmable gate arrays; Logic; Power dissipation; Semiconductor device modeling;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206270
