Title :
Low-power CMOS circuit techniques for motion estimators
Author :
Enomoto, Tadayoshi ; Ei, Tomomi
Author_Institution :
Graduate Sch. of Sci. & Eng. Inf. & Syst. Eng. Course, Chuo Univ., Tokyo, Japan
Abstract :
To drastically reduce the active power (PAT) and the stand-by power (PST) of the CMOS motion estimator (ME), several power reduction techniques were developed. They were circuit architectures that were able to reduce supply voltages (VD) and numbers of logic gates, a fast motion estimation algorithm, and a leakage current reduction circuit. A 0.13-μm CMOS accumulation-type ME (AME) LSI has been developed by using those techniques. At clock frequency of 220 MHz and VD of 0.73 V, PAT was reduced to 51.2 μW, which was 16.3% that of a conventional AME. PST was 9.92 nW, which was 9.58% that of the conventional AME.
Keywords :
CMOS digital integrated circuits; digital signal processing chips; image coding; integrated circuit design; leakage currents; logic design; low-power electronics; motion estimation; pipeline processing; 0.13 micron; 0.73 V; 220 MHz; 51.2 muW; 9.92 nW; CMOS accumulation-type ME LSI; MPEG-4 encoder; active power; circuit architectures; clock frequency; fast motion estimation algorithm; leakage current reduction circuit; low-power CMOS circuit techniques; motion estimators; numbers of logic gates; pipeline stage; power reduction techniques; stand-by power; supply voltages; CMOS logic circuits; CMOS technology; Clocks; Frequency; Large scale integration; Leakage current; Logic circuits; Logic gates; Motion estimation; Voltage;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206299
