Noise-constrained interconnect optimization for nanometer technologies

Wide, thick wiring, clock frequency in the GHz range will require interconnection analysis to consider inductance and inductive coupling effects on interconnect delay and noise. Analytical expressions are preferred because simulation is always expensive and ineffective in use with modem designs containing millions of transistors and wires. However, analytical expressions are not sufficiently accurate and do not consider all of interconnect and driver parameters. In this paper, we try to merge between analytical models and a table lookup approach to easily get the crosstalk peak noise, as well as impact of coupling on aggressor delay. The pulse width of the crosstalk noise, which is of similar importance for circuit performance as the peak amplitude, is also measured. We consider parameters like spacing, length, coupling length, place of overlap (near driver or receiver side), frequency, direction of the signals, load capacitance, rise time of the inputs, wire width for both the aggressors and the victim wires. Also, we consider parameters like shields and shield width to decrease the inductive coupling.