Interface specification and synthesis for VHDL processes

Author

Gutberlet, P. ; Rosenstiel, W.

Author_Institution

Forschungszentrum Inf., Karlsruhe, Germany

fYear

1993

Firstpage

152

Lastpage

157

Abstract

A method is presented to separate the algorithmic specification from the specification of the protocol level allowing a hierarchical design. A VHDL subset and a methodology for the specification is defined. The authors show the target architecture to merge the different levels into one synchronous data path. They present the algorithm especially dealing with the interface part of the specification. Finally, some results are given

Keywords

formal specification; hardware description languages; logic CAD; protocols; timing; VHDL; algorithmic specification; behavioural synthesis; heuristic estimation; hierarchical design; interface specification; protocol level; scheduling; synchronous data path; target architecture; Circuit synthesis; Clocks; Control system synthesis; Delay; High level synthesis; Petri nets; Protocols; Signal synthesis; Specification languages; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European

Conference_Location

Hamburg

Print_ISBN

0-8186-4350-1

Type

conf

DOI

10.1109/EURDAC.1993.410630

Filename

410630

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1563294