MPSoC architecture for Component Level Parallelism of H.264/AVC intra prediction encoding chain on SoCLib platform

Nowadays, higher resolutions and faster processing time are more and more demanded in the field of video applications. Thus, algorithmic complexity of the encoder and its performances are the main penalties for such requirements. Recent woks show the efficiency of using the Multiprocessor System on Chip (MPSoC) technology to overcome the shortcomings of real-time processing with a single processor. We contribute to this challenge by proposing a MPSoC architecture for the intra prediction encoding chain, which is an important part of the H.264/AVC video standard. This MPSoC architecture is based on Component Level Parallelism (CLP) approach. This approach is tested and evaluated on SoCLib platform for virtual prototyping of MPSoC architectures. Experimental results show a gain of 32% in encoding speed when using two processors (CPUs), and enabling minimum memory size and MPSoC surface.