DocumentCode :
1563782
Title :
JOGM: A CMOS cell layout style using jogged transistor gates
Author :
Hindmarsh, Ronald D.
Author_Institution :
Inst. fur Tech. Inf., Tech. Univ. Berlin, Germany
fYear :
1993
Firstpage :
184
Lastpage :
188
Abstract :
A new width minimizing layout style called jogged gate matrix (JOGM) for CMOS cells is described. The traditional gate matrix layout style is modified by inserting 45° jogs into transistor gates. Thus, JOGM improves CMOS cell width by 23% to 31% in comparison to traditional gate matrix layout. An approach for automatic layout generation is suggested
Keywords :
CMOS logic circuits; cellular arrays; circuit layout CAD; integrated circuit design; integrated circuit layout; CMOS cell layout; automatic layout generation; diffusion topology macro; jogged gate matrix; jogged transistor gates; CMOS logic circuits; Circuit synthesis; Design automation; Design optimization; Digital circuits; Logic design; MOS devices; Parasitic capacitance; Switching circuits; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-4350-1
Type :
conf
DOI :
10.1109/EURDAC.1993.410635
Filename :
410635
Link To Document :
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