Title :
Partitioning of code for a massively parallel machine
Author :
Ball, Michael ; Cifuentes, Cristina ; Bairagi, Deepankar
Author_Institution :
Sun MicroSystems, Menlo Park, CA, USA
Abstract :
Code partitioning is the problem of dividing sections of code among a set of processors for execution in parallel taking into account the communication overhead between the processors. Code partitioning of large amounts of code onto numerous processors requires variations to the classical partitioning algorithms, in part due to the memory and time requirements to partition a large set of data, but also due to the nature of the target machine and multiple constraints imposed by its architectural features. We present our experience in the design of enhancements to the classical multilevel k-way partitioning algorithm to deal with large graphs of over 1 million nodes, 5 constraints, and nodes of irregular size. Our algorithm was implemented to produce code for a massively parallel machine of up to 40,000 processors, and forms part of a hardware description language compiler. The algorithm and the compiler were tested on RTL designs for a next generation SPARC(R) processor. We present performance results and comparisons for partitioning multiprocessor hardware designs.
Keywords :
graph theory; hardware description languages; parallel algorithms; parallel machines; program compilers; RTL designs; Verilog compiler; code partitioning; hardware description language compiler; multilevel k-way partitioning algorithm; multiprocessor hardware design partitioning; next generation SPARC processor; parallel machine; Parallel architectures; Parallel machines;
Conference_Titel :
Parallel Architecture and Compilation Techniques, 2004. PACT 2004. Proceedings. 13th International Conference on
Print_ISBN :
0-7695-2229-7
DOI :
10.1109/PACT.2004.1342556