Title :
Very high efficiency VLSI chip-pair for full search block matching with fractional precision
Author :
Yang, Kun-Min ; Sun, Ming-Ting ; Wu, Lance ; Chuang, I.-F.G.
Author_Institution :
Bell Commun. Res., Morristown, NJ, USA
Abstract :
VLSI architecture design and implementation of a chip pair for the motion compensation full search block matching algorithm are described. This pair of ASICs (application-specific integrated circuits) is motivated by the intensive computational demands for performing motion compensation in real time. They have been developed to calculate fractional motion vectors with quarter-pel precision. The VLSI architecture is based on some special data-flow designs that allow sequential inputs but perform parallel processing with 100% efficiency for integer motion vector estimation and nearly 100% for fractional motion vector estimation. The chip-pair design has been laid out and simulated using a silicon compiler tool, and the chip statistics are summarized. Testing circuitry is included to increase the observability of the chips
Keywords :
VLSI; application specific integrated circuits; picture processing; video signals; ASIC; VLSI architecture design; VLSI chip pair; application-specific integrated circuits; data-flow designs; fractional motion vector estimation; full search block matching algorithm; integer motion vector estimation; parallel processing; real time motion compensation; sequential inputs; testing circuitry; Algorithm design and analysis; Application specific integrated circuits; Circuit simulation; Circuit testing; Computer architecture; Motion compensation; Motion estimation; Parallel processing; Silicon compiler; Very large scale integration;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1989. ICASSP-89., 1989 International Conference on
Conference_Location :
Glasgow
DOI :
10.1109/ICASSP.1989.266960
