DocumentCode :
1565533
Title :
A new logic minimization method for multiplexor-based FPGA synthesis
Author :
Jacobi, Ricardo Pezzuol ; Trullemans, Anne-Marie
Author_Institution :
Lab. de Microelectron., Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium
fYear :
1993
Firstpage :
312
Lastpage :
317
Abstract :
A new method was presented for the minimization of incompletely specified functions using MBDs (modified binary decision diagrams: ROBDDs with a don´t care terminal). The cost function to be minimized is the MBD size, which is an important factor in the case of FPGA synthesis. The method developed is based on a subgraph matching target to reduce the number of nodes of a MBD. The matching relies on the presence of a third terminal value X (don´t care) in the MBD in order to represent an incompletely specified function in a single graph. The authors have compared the new method with ESPRESSO with respect to MBD size reduction and multiplexor based synthesis. The results obtained empirically confirm the initial hypothesis that two-level minimization techniques are inadequate for this purpose, and also show the efficiency of the proposed algorithm
Keywords :
field programmable gate arrays; graph theory; logic CAD; logic design; minimisation; programmable logic arrays; ESPRESSO; cost function; incompletely specified function; logic minimization; modified binary decision diagrams; multiplexor based synthesis; multiplexor-based FPGA synthesis; subgraph matching target; two-level minimization; Boolean functions; Circuit synthesis; Cost function; Data structures; Field programmable gate arrays; Identity-based encryption; Logic functions; Minimization methods; Optimization methods; Programmable logic arrays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-4350-1
Type :
conf
DOI :
10.1109/EURDAC.1993.410656
Filename :
410656
Link To Document :
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