Title :
Software solutions for the Viterbi algorithm
Author :
Ikekawa, Masao ; Kuroda, Ichiro
Author_Institution :
Inf. Technol. Res. Labs., NEC Corp., Kawasaki, Japan
Abstract :
Efficient software implementations of the Viterbi algorithm on two new generation processors, μPD7701x and V830 are discussed. μPD7701x is a 16-bit fixed point general purpose DSP which includes eight 40-bit general purpose registers, highly parallel operation capability, and conditional execution capability. V830 is a 32-bit RISC processor which has a multiply-accumulator and other special instructions for multimedia signal processing. These features enable effective implementations on both processors. The Viterbi decoders for rate 1/2 convolutional code are implemented on these processors and are two times faster than on conventional type DSPs
Keywords :
Viterbi decoding; convolutional codes; digital arithmetic; digital signal processing chips; multimedia communication; parallel architectures; reduced instruction set computing; μPD7701x; 16 bit; 32 bit; 40 bit; RISC processor; V830; Viterbi algorithm; Viterbi decoders; conditional execution capability; fixed point general purpose DSP; highly parallel operation capability; multimedia signal processing; multiply-accumulator; rate 1/2 convolutional code; software implementations; Application software; Automata; Character recognition; Convolution; Convolutional codes; Decoding; Digital signal processing; Reduced instruction set computing; Signal processing algorithms; Viterbi algorithm;
Conference_Titel :
VLSI Signal Processing, VIII, 1995. IEEE Signal Processing Society [Workshop on]
Conference_Location :
Sakai
Print_ISBN :
0-7803-2612-1
DOI :
10.1109/VLSISP.1995.527480
