Title :
Managing verification error traces with Bounded Model Debugging
Author :
Safarpour, Sean ; Veneris, Andreas ; Najm, Farid
Author_Institution :
Vennsa Technol. Inc., Toronto, ON, Canada
Abstract :
Managing long verification error traces is one of the key challenges of automated debugging engines. Today, debuggers rely on the iterative logic array to model sequential behavior which drastically limits their application. This work presents bounded model debugging, an iterative, systematic and practical methodology to allow debuggers to tackle larger problems than previously possible. Based on the empirical observation that errors are excited in temporal proximity of the observed failures, we present a framework that improves performance by up to two orders of magnitude and solve 2.7x more problems than a conventional debugger.
Keywords :
formal verification; iterative methods; logic arrays; logic testing; bounded model debugging; iterative logic array; verification error traces; Circuit simulation; Clocks; Costs; Debugging; Engines; Error correction; Iterative methods; Logic arrays; Registers; Very large scale integration;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-5765-6
Electronic_ISBN :
978-1-4244-5767-0
DOI :
10.1109/ASPDAC.2010.5419816