DocumentCode :
1571375
Title :
Design of a two-capacitor sample & hold circuit using a two-stage OTA with hybrid cascode compensation
Author :
Zangeneh, Mahmoud ; Aghababa, Hossein ; Forouzandeh, Behjat
Author_Institution :
Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran
fYear :
2009
Firstpage :
493
Lastpage :
498
Abstract :
This paper presents a well-established low power sample & hold circuitry, implemented in 180-nm CMOS technology. This circuit uses a systematic and optimal design of hybrid cascode compensation method which is used in fully differential two-stage CMOS operational transconductance amplifiers (OTAs). The circuit achieves minimum SNR of 74 dB in all corner cases. Also average current dissipation of the whole circuit is measured to be 7.1 mA in Typical-Typical corner case. SNR and total current dissipation of the circuit is calculated and listed in different corner cases. Although the sample and hold circuit meets the requirements of SNR specifications, this success does not seem to be outstanding. However, small amount of current dissipation which comes from the low-power OTA configuration is a great success.
Keywords :
CMOS analogue integrated circuits; capacitors; compensation; operational amplifiers; sample and hold circuits; CMOS technology; Typical-Typical corner case; current 7.1 mA; current dissipation; hybrid cascode compensation; hybrid cascode compensation method; operational transconductance amplifiers; size 180 nm; two-capacitor sample and hold circuit; two-stage OTA; CMOS technology; Clocks; Current measurement; Differential amplifiers; Frequency; Operational amplifiers; Signal processing; Switched capacitor circuits; Switching circuits; Transconductance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuit Theory and Design, 2009. ECCTD 2009. European Conference on
Conference_Location :
Antalya
Print_ISBN :
978-1-4244-3896-9
Electronic_ISBN :
978-1-4244-3896-9
Type :
conf
DOI :
10.1109/ECCTD.2009.5275029
Filename :
5275029
Link To Document :
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