Minimum leakage vector computation using weighted partial MaxSAT

Aggressive scaling of CMOS technology has enabled faster and smaller designs but has posed new challenges. In the deep-submicron era, leakage power has become a major contributor to the overall power dissipation of an IC. In this paper, we present a weighted partial Max-SAT (WPMax-SAT) based approach to find the minimum leakage vector (MLV) of a combinational design. In its exact form, this technique computes the input vector which gives the lowest leakage for a combinational design. For large designs, the exact WPMax-SAT based technique may require large runtimes. Therefore, for such designs, the exact technique is run for a fixed amount of time followed by a guided random search around the best leakage vector computed by the WPMax-SAT solver. We also present a variant of our approach in which the MLV is generated by including the effect of random variations in leakage due to variations in process, voltage and temperature (PVT). Experimental results on ISCAS85 and MCNC91 benchmark circuits show that for larger circuits on average, our method reports a 3.62% improvement in mean, 4.20% improvement in standard deviation and 3.67% improvement in μ + 3*σ leakage of the circuit under PVT variations, compared to a random vector based MLV determination approach (with the same runtime as the random vector based approach).