A high-accuracy, low-power consumption switched-capacitor interface of differential capacitance transducers

Author

Ogawa, Satomi

Author_Institution

Fac. of Educ. Human Sci., Univ. of Yamanashi, Kofu, Japan

fYear

2010

Firstpage

684

Lastpage

687

Abstract

A high-accuracy and low-power consumption interface of differential capacitance transducer based on switched-capacitor (SC) sample/hold (S/H) circuit including a fully-differential subtractor is presented. This interface reduces the nonlinear error by means of double sampling and does not require component matching. Performances of the proposed interface are simulated by HSPICE using a 0.35 μm n-well CMOS process parameter. The results have demonstrated that the proposed interface offers increased linearity and lower power consumption.

Keywords

CMOS integrated circuits; capacitive sensors; circuit simulation; low-power electronics; switched capacitor networks; HSPICE; differential capacitance transducers; double sampling; fully-differential subtractor; high-accuracy low-power consumption switched-capacitor interface; n-well CMOS process parameter; size 0.35 mum; switched-capacitor sample/hold circuit; Capacitance; Capacitors; Circuit simulation; Clocks; Energy consumption; Sampling methods; Switching circuits; Timing; Transducers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on

Conference_Location

Seattle, WA

ISSN

1548-3746

Print_ISBN

978-1-4244-7771-5

Type

conf

DOI

10.1109/MWSCAS.2010.5548727

Filename

5548727