Reconstructing Control Flow in Modulo Scheduled Loops

Software pipelining is a loop optimization technique used to exploit instruction level parallelism in the loop. EPIC architectures, such as Intel IA-64 (Itanium) provide extensive hardware support for software pipelining to generate compact and highly parallel code. However it transforms explicit conditional branches into implicit control flow based on the information of the guard registers. It is difficult to reconstruct precise control flow from the optimized code. This paper describes an approach to reconstruct implicit control flow in modulo scheduled loops and thereby improve the quality of reverse engineering optimized executables. We also demonstrate the effectiveness of this approach through experiment results.