Performance impact of post-regrowth channel etching on InGaAs MOSFETs having MOCVD source-drain regrowth

Given low interface trap densities and low access resistances, InGaAs MOSFETs can provide greater on-state current than silicon MOSFETs at the same effective oxide thickness (EOT), and are thus strong candidates for use in VLSI.¹ Transconductance as high as 2.1 mS/μm (V_ds=0.5 V) with 115 mV/decade (V_ds=0.5 V) subthreshold swing has been reported² in planar III-V MOSFETs using a gate recess etch through the N+ InGaAs contact layer. It remains to be established whether the necessary etch depth control can be obtained at VLSI integration scales and 10-20 nm gate lengths. Using self-aligned regrowth of the N+ source and drain, III-V MOSFETs can be fabricated without requiring this gate recess etch;³ 1.9 mS/μm (V_d =1 V) with 116 mV/decade (V_ds=0.05 V) subthreshold swing was reported in a 55 nm L_g InGaAs MOSFET with MOCVD source-drain regrowth.⁴ Note that no post-regrowth etching of the channel surface is reported in (4). We have recently found⁵ that InGaAs MOSFETs using MBE source-drain regrowth, subthreshold swing and transconductance are substantially improved by removing a 5 nm N+ InGaAs channel cap post-regrowth and immediately prior to gate dielectric deposition, suggesting damage to the channel surface during regrowth. Here, we report similar findings for MOCVD regrowth. We fabricated 65 nm L_g In₀.₅₃Ga_0.47As surface-channel MOSFETs in a gate-last process with self-aligned raised InGaAs S/D access regions formed by MOCVD regrowth. Removal of ~ 2.4 nm of the channel surface by digital etching improved the transconductance from 1.1 to 1.58 mS/μm (65 nm L_g V_d=0.5 V), and reduced the subthreshold swing from 326 to 110 mV/dec (1 μm L_g, V_ds=0.05 V). These results suggest that substantial surface damage arises, and must be addressed, in MOCVD reg- owth III-V MOSFET processes.