Atomistic tight-binding based evaluation of impact of gate underlap on source to drain tunneling in 5 nm gate length Si FinFETs

The excellent control over short channel effects achievable using FinFETs have made them an attractive choice for realizing low-power and robust logic circuits and SRAMs in ultra-scaled technologies [1]. For deeply scaled gate lengths of the order of 5nm, increased direct source to drain tunneling (DSDT) is expected to contribute significantly to the off-state leakage current [2]. Gate underlap has been previously investigated as an effective way to reduce the thermionic component of leakage current since it increases the effective channel length. A variant of this, the asymmetric drain underlap was found to not only mitigate the leakage problem but also allowed for independent optimization of 6T SRAM read and write noise margins [3]. In this work, the impact of gate underlap on DSDT component of the off-state leakage current has been studied by using atomistic sp3d5s* tight binding based quantum ballistic coupled Poisson-NEGF transport simulations.