Title :
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through
Author_Institution :
Dept. of Inf. & Commun. Eng., Chaoyang Univ. of Technol., Taichung, Taiwan
Abstract :
In this brief, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based on post-layout simulation results using TSMC CMOS 90-nm technology, the proposed design outperforms the conventional P-FF design data-close-to-output (ep-DCO) by 8.2% in data-to-Q delay. In the mean time, the performance edges on power and power- delay-product metrics are 22.7% and 29.7%, respectively.
Keywords :
CMOS logic circuits; flip-flops; logic design; low-power electronics; TSMC CMOS technology; conventional P-FF design data-close-to-output; conventional explicit type P-FF design; conventional explicit-type pulse-triggered FF design; data-to-Q delay; explicit type pulse-triggered structure; long-discharging path problem; low-power FF design; low-power pulse-triggered flip-flop design; mean time; modified true-single-phase clock latch; post-layout simulation; power-delay-product metrics; signal feed-through; signal feed-through scheme; size 90 nm; Clocks; Delay; Latches; Power demand; Pulse generation; Switches; Transistors; Flip-flop (FF); low power; pulse-triggered;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2012.2232684
