Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?

Quasi delay-insensitive design is a promising solution for coping with contemporary silicon technology problems such as aggressive process variations and tight power budgets. However, one major barrier to its wider adoption is the lack of automated optimization techniques for building circuits using semi-custom methodologies. This paper proposes an innovative design flow that relies on the use of consolidated commercial EDA frameworks for synthesizing 1-of-n 4-phase quasi delay-insensitive circuits using Null Convention Logic. Asynchronous gates that are usually not supported by these frameworks are modelled as conventional logic gates, allowing synthesis tools to perform static timing analysis as well as pre- and post-mapped design optimizations, which can be specified by the designer using conventional timing constraints.