Title :
Interleaving partial bus-invert coding for low power reconfiguration of FPGAs
Author :
Yoo, Sungjoo ; Choi, Kiyoung
Author_Institution :
Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
fDate :
6/21/1905 12:00:00 AM
Abstract :
The authors propose a bus encoding scheme which partitions the configuration data sequence of an FPGA into sub-sequences and applies partial bus-invert coding to each sub-sequence to reduce the number of data bus transitions in reconfiguring the FPGA. Experimental results show that the proposed method gives 12.79%~17.06% more reduction of bus transitions on average compared with the conventional bus-invert coding, partial bus-invert coding, and the Beach coding
Keywords :
VLSI; encoding; field programmable gate arrays; logic design; low-power electronics; FPGA; bus encoding scheme; data bus transitions reduction; data sequence; interleaving technique; low power reconfiguration; partial bus-invert coding; sub-sequence; Capacitance; Decoding; Electronic mail; Encoding; Energy consumption; Field programmable gate arrays; Hardware; Interleaved codes; Potential well; Writing;
Conference_Titel :
VLSI and CAD, 1999. ICVC '99. 6th International Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5727-2
DOI :
10.1109/ICVC.1999.820997
