Title :
PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking
Author :
Wu, Shih-Chieh ; Wang, Chun-Yao
Author_Institution :
Dept. of Comput. Sci., Nat. Tsing Hua Univ., HsinChu
Abstract :
This paper describes an approximate approach for combinational equivalence checking. We propose an architecture such that a virtually-zero aliasing rate is obtained in a single-pass probability calculation. Furthermore, the aliasing rate can be easily configured in various precision by designers. We conduct experiments on a set of ISCAS´85 benchmarks. Experimental results show that with virtually-zero aliasing rate, for example, 10-74, our approach is more efficient than those exact approaches
Keywords :
combinational circuits; logic design; probability; ISCAS´85 benchmarks; PEACH; probabilistic combinational equivalence checking; single-pass probability calculation; virtually-zero aliasing rate; Automatic test pattern generation; Binary decision diagrams; Boolean functions; Circuit faults; Circuit simulation; Computer architecture; Computer science; Data structures; Probabilistic logic; Probability;
Conference_Titel :
Very Large Scale Integration, 2006 IFIP International Conference on
Conference_Location :
Nice
Print_ISBN :
3-901882-19-7
DOI :
10.1109/VLSISOC.2006.313212
