Heavy ion test results of RHBD standard cells and memory in a 110nm bulk CMOS process

Author

Cameron, Eric ; Miles, Lowell ; Whitaker, Shequi´lla ; Maki, Gary ; Shreve, Matthew

Author_Institution

ICs LLC, McCall, ID, USA

fYear

2014

fDate

1-8 March 2014

Firstpage

1

Lastpage

7

Abstract

This paper describes heavy ion testing and results gathered from a test chip produced in the ON Semiconductor 110nm process. Content on this test chip includes conventional CMOS standard cells augmented with Radiation Hardened By Design (RHBD) library elements and dual port SRAM with error correction code (ECC) developed specifically for SEE concerns and high performance operation. Favorable test results are presented showing SEE performance of the Self Restoring Logic (SRL) cell to 140 MeVcm²/mg onset LET for upsets. Additionally, SRL based polynomial counters performed flawlessly at 700MHz to an LET of 78 MeVcm²/mg. SEL protection of the bulk CMOS process using the special support cells is described. SRL flip flop results are compared to legacy DICE and SERT flip flop architecture results.

Keywords

CMOS logic circuits; CMOS memory circuits; SRAM chips; error correction codes; flip-flops; integrated circuit testing; logic circuits; logic testing; polynomials; radiation hardening (electronics); radiofrequency integrated circuits; DICE; ECC; LET; ON semiconductor process; RHBD CMOS standard cell; SEE; SERT flip flop architecture; SRL cell; SRL flip flop; bulk CMOS process; dual port SRAM; error correction code; frequency 700 MHz; heavy ion testing; library elements; polynomial counter; radiation hardened by design; self restoring logic cell; size 110 nm; Clocks; Field programmable gate arrays; Polynomials; Radiation detectors; Random access memory; Shift registers; Standards;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace Conference, 2014 IEEE

Conference_Location

Big Sky, MT

Print_ISBN

978-1-4799-5582-4

Type

conf

DOI

10.1109/AERO.2014.6836526

Filename

6836526