Title :
A chip-level electrothermal simulator for temperature profile estimation of CMOS VLSI chips
Author :
Cheng, Yi-Kan ; Teng, Chin-Chi ; Dharchoudhury, Abhijit ; Rosenbaum, Elyse ; Kang, Sung-Mo
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
In this paper, we present a chip-level electrothermal simulator, ILLIADS-T. It aims at finding the steady-state CMOS VLSI chip temperature profile and the corresponding circuit performance. With this tool, temperature-related reliability problems of VLSI chips can be accurately predicted to guide the module placement, packaging, as well as the timing verification
Keywords :
CMOS logic circuits; VLSI; circuit analysis computing; combinational circuits; integrated circuit modelling; integrated circuit reliability; sequential circuits; temperature distribution; thermal analysis; timing; CMOS VLSI chips; ILLIADS-T; chip-level electrothermal simulator; circuit performance; temperature profile estimation; temperature-related reliability problems; timing verification; Circuit simulation; Computational modeling; Electrothermal effects; MOS devices; Packaging; Steady-state; Temperature; Timing; Ultra large scale integration; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.542090
