The effect of process variation on NBTI degradation in 90nm PMOS

This paper presents the effects of process variation on the Negative Bias Temperature Instabilities (NBTI) of a 90 nm PMOSFET. The process parameters which are varied in this work are the stress temperature and the hydrogen diffusivity. The effects on the fundamental device parameters namely the interface trap concentration, threshold voltage and the drain current had been studied utilizing the technology CAD (TCAD) Sentaurus Synopsys simulator. At elevated temperatures, the PMOS transistor shows a higher interface trap concentration and a considerable drift in the threshold voltage along with significant degradation in the drain current, when a large negative bias is applied.