Scheduling algorithm in datapath synthesis for long duration transient fault tolerance

As the advance in semiconductor technologies, transient faults caused by particle strike in combinational logic, so-called SETs, have become a matter of concern, and further it is predicted that such faults can span across more than one clock cycle. This paper presents a scheduling algorithm in high-level synthesis of long duration transient fault tolerant datapaths. On the basis of the properties of operational units for error correction and detection in behaviorally tripled module systems, we introduce the concept of forces among operations in unscheduled data-flow graphs, and propose a scheduling algorithm based on well-known force-directed scheduling. Experimental results show that the proposed scheduling algorithm can derive multi-cycle fault tolerant datapaths with small hardware resources compared with simply-tripled datapaths.