Zero skew clock routing algorithm for high performance ASIC systems

As the chip dimensions are growing and switching speed of circuit elements is increasing, the issues related to clock delay are becoming more important. As a result, clock routing problem has been extensively studied in recent years. Most of the research has concentrated on minimizing or eliminating clock skew. The problem of minimizing total wirelength and maintaining planarity has received little or no attention. The authors consider the problem of routing clock nets in high performance ASIC systems. They develop an algorithm which routes a planar clock tree with zero skew and minimal total wirelength. The proposed algorithm provides a tradeoff between total wavelength and planarity of the clock tree. The authors propose two clock routing approaches; First, they develop a clock routing algorithm, which achieves zero skew clock trees with minimal wirelength. The second approach results in planar clock trees with zero skew at the cost of larger wirelength. Experimental results show that the proposed algorithm produces zero skew trees which are planar and have up to 15% less wirelength than previous algorithms