DocumentCode :
1595321
Title :
Simulation of the test process for analogue integrated circuits
Author :
Povazanec, Juraj ; MUSIL, Vladislav ; Kaderka, Jiri
Author_Institution :
Fac. of IES, Leeds Univ., UK
Volume :
4
fYear :
1996
Firstpage :
711
Abstract :
The paper describes a new implementation of testing-algorithm model for analogue and mixed-signal circuits with neural network evaluation. The simulation system is programmable (different fault models, input stimuli, and different analyses), it covers a wide spectrum of test methods and desired post-process techniques. It is based on the possibilities of HSPICE and MATLAB to manage whole test simulation including the simulations of faulty or fault free circuits as well as post-processing by means of a neural network classifier. The approach takes into account tolerances deviations on parameters. The aim of this project is to model test techniques in order to classify their effectiveness in the sense of fault coverage. The system was verified on practical test tasks
Keywords :
analogue integrated circuits; circuit analysis computing; digital simulation; integrated circuit testing; mixed analogue-digital integrated circuits; neural nets; HSPICE; MATLAB; analogue integrated circuits; fault coverage; fault free circuits; faulty circuits; mixed-signal circuits; neural network classifier; neural network evaluation; post-process techniques; programmable simulation system; test process simulation; testing-algorithm model; tolerances deviations; Analog integrated circuits; Analytical models; Circuit faults; Circuit simulation; Circuit testing; Integrated circuit testing; MATLAB; Mathematical model; Neural networks; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
Type :
conf
DOI :
10.1109/ISCAS.1996.542123
Filename :
542123
Link To Document :
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