Title :
Tutorial on design for testability (DFT) "An ASIC design philosophy for testability from chips to systems"
Author :
Satish, Keshava Iyengar
Author_Institution :
VLSI Technology, Inc., San Jose, CA, USA
Abstract :
This is a comprehensive tutorial on DFT with emphasis on concepts of digital Application Specific Integrated Circuit (ASIC) testing incorporating boundary scan architecture in ASIC design. This tutorial covers discussion and features of Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1, Joint Test Action Group (JTAG) test technique, that can be implemented during design and development of digital ASIC and systems. These test techniques can be applied to test device mounted multi-layer Printed Circuit Boards (PCBs) and Multi Chip Modules (MCMs)
Keywords :
IEEE standards; application specific integrated circuits; automatic test software; boundary scan testing; built-in self test; design for testability; digital integrated circuits; fault diagnosis; integrated circuit testing; logic testing; multichip modules; printed circuit testing; ASIC design philosophy; ATPG; BIST; IEEE Standard 1149.1; JTAG technique; MCM; boundary scan architecture; design for testability; device mounted; digital logic; fault model; multilayer PCB; tutorial; Application specific integrated circuits; Circuit testing; Design engineering; Design for testability; Electronic equipment testing; Integrated circuit testing; Printed circuits; Standards development; System testing; Tutorial;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410825
