Glass isolated TSVs for MEMS

MEMS devices require wafer level hermetic encapsulation to protect the delicate moving structures and electrostatic/capacitive transducers from environmental influences. Encapsulation is most often done by bonding a encapsulating wafer to the MEMS wafer. Electrical contacts to the hermetic space are provided in the state of the art MEMS devices by horizontal interconnections across the bonding interface. It has been recognized that it would be beneficial to have vertical electrical vias through the encapsulating wafer. These would enable size reduction of the device, improved functionality due to shorter interconnections and utilization of WLCSP steps as a back-end operation. The advances of TSVs for ICs and interposers have benefitted some latest MEMS designs. However, there exists a much earlier approach to TSVs for MEMS in Vaisala company starting in mid-80´s. Alkaline borosilicate glass is a traditional MEMS material due to thermal expansion match with silicon and anodic bonding capability for wafer bonding. Therefore it was natural to use this glass also for TSV isolation. This method has been used for multi-axis accelerometers and gyro-sensors in VTI Technologies Oy (now Murata Electronics Oy). Mechanical machining by dicing saw or deep anisotropic silicon etching is used to form the mandrel, over which glass is casted by applying pressure at elevated temperature. The resulting glass surface is ground and polished to expose silicon on the front surface. The backside of the wafer is ground either before or after wafer bonding until glass becomes exposed. Isolated areas of silicon that penetrate through the wafer are thus created and they function as TSVs. Metal layers for electrodes, interconnections and gettering are applied on the glass surface. Also isolating layers are applied to prevent shorting and sticking between moving and stationary electrodes. Redistribution and contact layers are formed on the back surface. This technology offers great versatility- for both via isolation and wafer to wafer isolation. It produces extremely small parasitic capacitances and leakage currents. The weaknesses of the technology are due to the alkaline content of the glass: the process is not CMOS-compatible and the glass surface is prone to aging and humidity effects.