DocumentCode
1600441
Title
On customized decimation filter implementation
Author
Naviner, Linda A De B ; Naviner, Jean-François
Author_Institution
GET, Telecom Paris, France
Volume
1
fYear
2004
Firstpage
304
Abstract
This paper deals with customized implementation of decimation processors. Important aspects of design law decisions are considered under hardware impact point of view. Several implementation approaches and respective evaluations in terms of time and basic operators requirements are given as well as a summary of the steps involved in an ad hoc implementation.
Keywords
FIR filters; FIR filters; ad hoc implementation; basic operators requirements; customized decimation filter implementation; hardware impact point of view; time requirements; Clocks; Computer architecture; Costs; Decoding; Energy consumption; Error correction; Finite impulse response filter; Hardware; Receivers; Sampling methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Technology, 2004. IEEE ICIT '04. 2004 IEEE International Conference on
Print_ISBN
0-7803-8662-0
Type
conf
DOI
10.1109/ICIT.2004.1490304
Filename
1490304
Link To Document