A partitioning and storage based built-in test pattern generation method for synchronous sequential circuits

We describe a built-in test pattern generation method for synchronous sequential circuits based on partitioning and storage of test subsequences. Under this method, a set of subsequences Ψ is stored on-chip. On-chip test sequences are obtained by implementing a subset of the Cartesian product ΨxΨx···xΨ. The set Ψ is obtained by iterative partitioning of a precomputed test sequence T. The number of subsequences in Ψ is minimized at every iteration in order to reduce the final storage requirements, the test application time, and the computational effort required to produce the final set Ψ